Package structure and method for manufacturing the same

ABSTRACT

A package structure and a method for manufacturing a package structure are provided. The package structure includes a first wiring structure and at least one electronic device. The at least one electronic device is connected to the first wiring structure through at least two joint structures. The at least two joint structures respectively include different materials.

BACKGROUND 1. Field of the Disclosure

The present disclosure relates to a package structure, and amanufacturing method, and to a package structure including at least twojoint structures respectively including different materials, and amethod for manufacturing the same.

2. Description of the Related Art

Along with the rapid development in electronics industry and theprogress of semiconductor processing technologies, semiconductor chipsare integrated with an increasing number of electronic components toachieve better electrical performance and more functions. Accordingly,the semiconductor devices are provided with more structures of variousmaterials. As such, coefficient of thermal expansion (CTE) mismatchissues have become increasingly crucial to the manufacture ofsemiconductor packages including such semiconductor devices.

SUMMARY

In some embodiments, a package structure includes a first wiringstructure and at least one electronic device. The at least oneelectronic device is connected to the first wiring structure through atleast two joint structures. The at least two joint structuresrespectively include different materials.

In some embodiments, a package structure includes a first wiringstructure, a first electronic device, a second wiring structure, a lowerelectronic device, a molding compound and a substrate structure. Thefirst electronic device is connected to the first wiring structure. Thelower electronic device is disposed on the second wiring structure. Anactive surface of the lower electronic device is facing an activesurface of the first electronic device. The molding compoundencapsulates the lower electronic device. The first wiring structure isdeposed on the molding compound, and a bonding pad is deposed on thesecond wiring structure. The substrate structure is connected to thesecond wiring structure through at least two bonding structures. The atleast two bonding structures respectively include different materials.

In some embodiments, a method for manufacturing a package structureincludes the following operations: (a) providing a first wiringstructure; (b) providing a first electronic device; (c) bonding thefirst electronic device to the first wiring structure through a firstjoint structure under a first temperature; and (d) bonding the firstelectronic device to the first wiring structure through a second jointstructure under a second temperature, wherein the first temperature ishigher than the second temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of some embodiments of the present disclosure are readilyunderstood from the following detailed description when read with theaccompanying figures. It is noted that various structures may not bedrawn to scale, and dimensions of the various structures may bearbitrarily increased or reduced for clarity of discussion.

FIG. 1A illustrates a cross-sectional view of a package structureaccording to some embodiments of the present disclosure.

FIG. 1B illustrates a cross-sectional view of a package structureaccording to some embodiments of the present disclosure.

FIG. 2 illustrates an enlarged view of a portion of a package structureaccording to some embodiments of the present disclosure.

FIG. 3 illustrates a cross-sectional view of a package structureaccording to some embodiments of the present disclosure.

FIG. 4A illustrates a cross-sectional view of a package structureaccording to some embodiments of the present disclosure.

FIG. 4B illustrates a cross-sectional view of a package structureaccording to some embodiments of the present disclosure.

FIG. 5 illustrates an enlarged view of a portion of a package structureaccording to some embodiments of the present disclosure.

FIG. 6 illustrates a cross-sectional view of a package structureaccording to some embodiments of the present disclosure.

FIG. 7 illustrates a cross-sectional view of a package structureaccording to some embodiments of the present disclosure.

FIG. 8 illustrates a cross-sectional view of a package structureaccording to some embodiments of the present disclosure.

FIG. 9A illustrates a top view of a portion of a package structureaccording to some embodiments of the present disclosure.

FIG. 9B illustrates a top view of a portion of a package structureaccording to some embodiments of the present disclosure.

FIG. 9C illustrates a top view of a portion of a package structureaccording to some embodiments of the present disclosure.

FIG. 9D illustrates a top view of a portion of a package structureaccording to some embodiments of the present disclosure.

FIG. 10A, FIG. 10B, FIG. 10C, FIG. 10D, FIG. 10E and FIG. 10F illustratevarious stages of a method of manufacturing a package structureaccording to some embodiments of the present disclosure.

FIG. 11A, FIG. 11B and FIG. 11C illustrate various stages of a method ofmanufacturing a package structure according to some embodiments of thepresent disclosure.

FIG. 12A, FIG. 12B, FIG. 12C, FIG. 12D, FIG. 12E, FIG. 12F, FIG. 12G,FIG. 12H, FIG. 12I and FIG. 12J illustrate various stages of a method ofmanufacturing a package structure according to some embodiments of thepresent disclosure.

FIG. 13 illustrates an intermediate stage of a method of manufacturing apackage structure according to some embodiments of the presentdisclosure.

DETAILED DESCRIPTION

Common reference numerals are used throughout the drawings and thedetailed description to indicate the same or similar components.Embodiments of the present disclosure will be readily understood fromthe following detailed description taken in conjunction with theaccompanying drawings.

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to explain certain aspects of the present disclosure. These are,of course, merely examples and are not intended to be limiting. Forexample, the formation of a first feature over or on a second feature inthe description that follows may include embodiments in which the firstand second features are formed or disposed in direct contact, and mayalso include embodiments in which additional features may be formed ordisposed between the first and second features, such that the first andsecond features may not be in direct contact. In addition, the presentdisclosure may repeat reference numerals and/or letters in the variousexamples. This repetition is for the purpose of simplicity and clarityand does not in itself dictate a relationship between the variousembodiments and/or configurations discussed.

FIG. 1A illustrates a cross-sectional view of a package structure 1according to some embodiments of the present disclosure. The packagestructure 1 includes a first wiring structure 2, at least one electronicdevice (including, for example, a first electronic device 3 and a secondelectronic device 3B), at least one first joint structure 11, at leastone second joint structure 12, an encapsulant 13, and an underfill 15.

The first wiring structure 2 may include at least one dielectric layer(including, for example, dielectric layers 211, 212, 213, 214 and 215)and at least one circuit layer (including, for example, circuit layers221, 222, 223 and 224 formed of a metal, a metal alloy, or otherconductive material). The at least one circuit layer may be in contactwith the at least one dielectric layer. In some embodiments, thedielectric layer may be made of a cured photoimageable dielectric (PID)material such as epoxy or polyimide (PI) including photoinitiators. Inaddition, the dielectric layer may include no fibers (e.g., glassfibers). In some embodiments, the first wiring structure 2 may be abumping level redistribution structure. The circuit layers 221, 222, 223and 224 may be fan-out circuit layers or redistribution layers (RDLs),and an L/S of the circuit layers 221, 222, 223 and 224 may be less thanor equal to about 10 μm/about 10 about 5 μm/about 5 about 2 μm/about 2or less than or equal to about 1.8 μm/about 1.8 In some embodiments, thecircuit layers 221, 222, 223 and 224 are embedded in the dielectriclayers. In some embodiments, the circuit layers 221, 222, 223 and 224include horizontally connecting or extending circuit layers. The firstwiring structure 2 may further include a plurality of inner vias. Theinner vias are disposed between the circuit layers for electricallyconnecting the circuit layers. In some embodiments, each inner via andthe corresponding circuit layer may be formed integrally as a monolithicor one-piece structure. The inner vias may have a taperedcross-sectional shape.

The first electronic device 3 and the second electronic device 3B areconnected to the first wiring structure 2 through the joint structures11, 12. In some embodiments, the first electronic device 3 and thesecond electronic device 3B are arranged side by side. In someembodiments, the first electronic device 3 and the second electronicdevice 3B may independently be or include an active component such as anapplication specific IC (ASIC), a memory component such as a highbandwidth memory (HBM) component or another active component. In someembodiments, the first electronic device 3 may be an applicationspecific IC (ASIC), and the second electronic device 3B may be a highbandwidth memory (HBM). In some embodiments, as shown in FIG. 1A, thepackage structure 1 includes two electronic devices (e.g., the firstelectronic device 3 and the second electronic device 3B), but thepresent disclosure is not limited thereto.

The first joint structure 11 and the second joint structure 12respectively include different materials. In some embodiments, the firstjoint structure 11 includes a first material, and the second jointstructure 12 includes a second material different from the firstmaterial. In some embodiments, a melting point of the first material ishigher than a melting point of the second material. In some embodiments,the first material includes a gold-tin (AuSn) alloy, and the secondmaterial includes copper (Cu). In some embodiments, the first materialincludes silver (Ag) paste, copper (Cu) paste, or a combination thereof,and the second material includes tin (Sn).

In a comparative embodiment, the CTE-mismatch issue caused by thedifference between the CTE of a wiring structure and the CTE of anelectronic device may cause different deformation levels betweendifferent structures and thereby may cause serious warpage to a packagestructure. In comparison, according to some embodiments of the presentdisclosure, the design of the two joint structures 11, 12 respectivelyincluding different materials can provide different stress on differentlocations within the package structure 1, particularly between the firstwiring structure 2 and the electronic device (e.g., the first electronicdevice 3 and/or the second electronic device 3B), and such difference instress can compensate the strain resulted from the CTE-mismatch withinthe package structure 1. Therefore, the bonding strength may beimproved, the overall structure of the package structure 1 may be morestable, and the quality as well as the performance of the packagestructure 1 may be improved.

In some embodiments, the first joint structure 11 includes a first bump111 disposed on the first electronic device 3 (or the second electronicdevice 3B). In some embodiments, the first joint structure 11 includes afirst pad 113 disposed in the first wiring structure 2. In someembodiments, the first pad 113 may be a portion of the circuit layer221. In some embodiments, the first joint structure 11 includes a firstsolder 112 disposed between the first wiring structure 2 and a bump ofthe first electronic device 3. In some embodiments, the first solder 112is disposed between the first pad 113 and the first bump 111. In someembodiments, the first bump 111, the first solder 112, and/or the firstbump 113 includes the first material. In some embodiments, the firstjoint structure 11 may be a dummy connecting component. In some otherembodiments, the first joint structure 11 may be connected to a groundpad and/or a power pad. According to some embodiments of the presentdisclosure, I/O counts are higher in the region including a power padand/or a ground pad, the first joint structures 11 including the firstmaterial can further apply stress on the chosen region to balance thestrain and reduce the warpage level.

In some embodiments, the second joint structure 12 includes a secondbump 121 disposed on the electronic device 3 (or the second electronicdevice 3B). In some embodiments, the second joint structure 12 includesa second pad 123 disposed in the first wiring structure 2. In someembodiments, the second pad 123 may be a portion of the circuit layer221. In some embodiments, the second joint structure 12 includes asecond solder 122 disposed between the first wiring structure 2 and abump of the first electronic device 3. In some embodiments, the secondsolder 122 is disposed between the second pad 123 and the second bump121. In some embodiments, the second bump 121, the second solder 122,and/or the second bump 123 includes the second material.

In some embodiments, the first bump 111 of the first joint structure 11includes the first material, and the second bump 121 of the second jointstructure 12 includes the second material. In some embodiments, thefirst material of the first bump 111 may be or include a gold-tin (AuSn)alloy, and the second material of the second bump 121 may be or includecopper (Cu).

In some embodiments, the first solder 112 of the first joint structure11 includes the first material, and the second solder 122 of the secondjoint structure 12 includes the second material. In some embodiments,the first material of the first solder 112 may be or include silver (Ag)paste, copper (Cu) paste, or a combination thereof, and the secondmaterial of the second solder 122 may be or include tin (Sn).

The underfill 15 is disposed in a space between the first wiringstructure 2 and the electronic device(s) (e.g., the first electronicdevice 3 and the second electronic device 3B) to cover and protect thefirst joint structure 11 and the second joint structure 12. In someembodiments, the underfill 15 directly contacts the first jointstructure 11 and the second joint structure 12.

The encapsulant 13 encapsulates the electronic device(s) (e.g., thefirst electronic device 3 and the second electronic device 3B) and theunderfill 15. In some embodiments, the encapsulant 13 exposes a surface31 (also referred to as “an upper surface”) of the electronic device 3.In some embodiments, a surface 131 (also referred to as “an uppersurface”) of the encapsulant 13 is substantially coplanar with thesurface 31 of the surface 31 of the electronic device 3. In someembodiments, the encapsulant 13 may be or include a molding compound.

FIG. 1B illustrates a cross-sectional view of a package structure 1′according to some embodiments of the present disclosure. The packagestructure 1′ is similar to the package structure 1 shown in FIG. 1A,except that the first joint structure 11 of the package structure 1′further includes a first pillar 114 disposed on the first pad 113. Insome embodiments, the second joint structure 12 of the package structure1′ further includes a second pillar 124 disposed on the second pad 123.

FIG. 2 illustrates an enlarged view of a portion of a package structureaccording to some embodiments of the present disclosure. In someembodiments, FIG. 2 illustrates an enlarged view of a portion “A” of thepackage structure 1 shown in FIG. 1A.

As shown in FIG. 2, the first solder 112 is disposed between anddirectly contacts the first bump 111 and the first pad 113. In someembodiments, the first bump 111 directly contacts the second solder 112and a surface 32 (also referred to as “a bottom surface”) of the firstelectronic device 3. The surface 32 of the first electronic device 3 maybe an active surface.

In a comparative embodiment, the CTE-mismatch issue caused by thedifference between the CTE of a wiring structure and the CTE of anelectronic device may easily cause serious warpage in the manufacturingprocess of the package structure, and such warpage may render thesolders deform or even detach. In contrast, according to someembodiments of the present disclosure, the design of the first materialof the first joint structures 11 has a higher melting point than thesecond material of the second joint structures 12, the first jointstructures 11 may be formed on chosen local regions to stably fix therelative position of the first wiring structure 2 and the electronicdevice(s) (e.g., the first electronic device 3 and the second electronicdevice 3B) under a relatively high processing temperature, and then thesecond joint structures 12 may be formed under a relatively lowertemperature performed for a relatively longer time, which facilitatesthe formation of intermetallic compound (IMC), such that the overallbonding strength of the package structure 1 may be increased.

FIG. 3 illustrates a cross-sectional view of a package structure 1 aaccording to some embodiments of the present disclosure. The packagestructure 1 a is similar to the package structure 1 shown in FIG. 1A,except that the package structure 1 a further includes a patterned masklayer 4.

As shown in FIG. 3, in some embodiments, the patterned mask layer 4 isdisposed on the surface 31 of the first electronic device 3 (or an uppersurface the second electronic device 3B), and the surface 31 (or theupper surface of the second electronic device 3B) is facing away fromthe first wiring structure 2. In some embodiments, the patterned masklayer 4 is further disposed on the surface 131 of the encapsulant 13. Insome embodiments, the patterned mask layer 4 directly contacts thesurface 31 of the first electronic device 3 (or the upper surface of thesecond electronic device 3B). In some embodiments, the patterned masklayer 4 directly contacts the surface 131 of the encapsulant 13.

In some embodiments, the patterned mask layer 4 defines at least oneopening 401. In some embodiments, the opening 401 of the patterned masklayer 4 is disposed right above the first joint structure 11. In someembodiments, the first joint structure 11 may be disposed within aprojection of the opening 401 of the patterned mask layer 4.

In some embodiments, the patterned mask layer 4 may be or include asputtered patterned metal. In some embodiments, the patterned mask layer4 may be or include a Ti/Cu/Ti multilayer or a Ti/Cu/stainless steelmultilayer. In some embodiments, the patterned mask layer 4 may have athickness of about 10 μm. According to some embodiments of the presentdisclosure, the patterned mask layer 4 including a metal material may bebeneficial to increasing the heat dissipation ability.

FIG. 4A illustrates a cross-sectional view of a package structure 1 baccording to some embodiments of the present disclosure. The packagestructure 1 b is similar to the package structure 1 shown in FIG. 1,except for the structure of the first joint structure 11A.

In some embodiments, as shown in FIG. 4A, the first joint structure 11Aincludes a first bump 111A disposed on the first electronic device 3 (orthe second electronic device 3B), a first pad 113 disposed in the firstwiring structure 2, and a first solder 112A disposed between the firstpad 113 and the first bump 111A. In some embodiments, the first jointstructure 11A further includes a first conductive layer 114 between thefirst pad 113 and the first solder 112A. In some embodiments, the firstconductive layer 114 may be referred to as under bump metallization(UBM). In some embodiments, the first bump 111A, the first solder 112A,the first conductive layer 114, and/or the first pad 113 includes thefirst material, and the second bump 121, the second solder 122, and/orthe second pad 123 includes the second material.

In some embodiments, as shown in FIG. 4A, the first joint structure 11Aand the second joint structure 12 have different structures. In someembodiments, the first bump 111A and the second bump 121 have differentshapes. For example, the first bump 111A has a height that is greaterthan a height of the second bump 121. In some embodiments, the firstsolder 112A and the second solder 122 have different shapes.

In some embodiments, the first material of the first bump 111A may be orinclude a gold-tin (AuSn) alloy, and the second material of the secondbump 121 may be or include copper (Cu). In some embodiments, the firstmaterial of the first conductive layer 114 may be or include a gold-tin(AuSn) alloy. In some embodiments, the first solder 112A and the secondsolder 122 may both be or include tin (Sn).

FIG. 4B illustrates a cross-sectional view of a package structure 1 b′according to some embodiments of the present disclosure. The packagestructure 1 b′ is similar to the package structure 1 b shown in FIG. 4A,except that the second joint structure 12 of the package structure 1 b′further includes a second pillar 124 disposed on the second pad 123. Insome embodiments, the second pillar 124 of the second joint structure 12includes the second material. In some embodiments, the second materialof the second pillar 124 may be or include copper (Cu).

FIG. 5 illustrates an enlarged view of a portion of a package structureaccording to some embodiments of the present disclosure. In someembodiments, FIG. 5 illustrates an enlarged view of a portion “B” of thepackage structure 1 b shown in FIG. 4A.

As shown in FIG. 5, in some embodiments, the first solder 112A extendson a portion of a sidewall of the first bump 111A. In some embodiments,the first solder 112A covers a portion of a sidewall of the first bump111A. In some embodiments, the first solder 112A surrounds a portion ofa sidewall of the first bump 111A. In some embodiments, the first solder112A is further filled within a space defined by the first bump 111A andthe first conductive layer 114.

As shown in FIG. 5, in some embodiments, the first conductive layer 114may define a recess portion that is concave towards the first wiringstructure 2. In some embodiments, a portion of the first bump 111A is inthe recess portion of the first conductive layer 114. In someembodiments, a portion of the first solder 112A is in the recess portionof the first conductive layer 114. In some embodiments, the bottomcorners of the first bump 111A directly contact the inner slant surfaceof the recess portion of first conductive layer 114. In someembodiments, the first conductive layer 114 directly contacts the firstsolder 112A. In some embodiments, the first bump 111A and the firstconductive layer 114 define a space within the recess portion of thefirst conductive layer 114.

FIG. 6 illustrates a cross-sectional view of a package structure 1 caccording to some embodiments of the present disclosure. The packagestructure 1 c is similar to the package structure 1 b shown in FIG. 4A,except that the package structure 1 c further includes a patterned masklayer 4.

As shown in FIG. 6, in some embodiments, the patterned mask layer 4 isdisposed on the surface 31 of the first electronic device 3 (or an uppersurface of the second electronic device 3B), and the surface 31 (or theupper surface of the second electronic device 3B) is facing away fromthe first wiring structure 2. In some embodiments, the patterned masklayer 4 is further disposed on the surface 131 of the encapsulant 13. Insome embodiments, the patterned mask layer 4 directly contacts thesurface 31 of first the electronic device 3 (or the upper surface of thesecond electronic device 3B). In some embodiments, the patterned masklayer 4 directly contacts the surface 131 of the encapsulant 13.

In some embodiments, the patterned mask layer 4 defines at least oneopening 401. In some embodiments, the opening 401 of the patterned masklayer 4 is disposed right above the first joint structure 11A. In someembodiments, the first joint structure 11A may be disposed within aprojection of the opening 401 of the patterned mask layer 4.

FIG. 7 illustrates a cross-sectional view of a package structure 1 daccording to some embodiments of the present disclosure. The package 1 dincludes a first wiring structure 2, a first electronic device 3, asecond electronic device 3B, a lower electronic device 3A, a substratestructure 5, at least one first joint structure 11, at least one secondjoint structure 12, an encapsulant 13, an underfill 15, a firstelectrical path 33, a second electrical path 34, a second wiringstructure 41, a molding compound 43, an underfill 45, and at least twobonding structures 51, 52. In some embodiments, the first wiringstructure 2, the first electronic device 3, the second electronic device3B, the first joint structure 11, the second joint structure 12, theencapsulant 13 and the underfill 15 are similar to those shown inprevious drawing (e.g., FIG. 1A, FIG. 2, FIG. 4A, and FIG. 5), and thedetails of which are omitted hereinafter.

The lower electronic device 3A is disposed on the second wiringstructure 41. In some embodiments, an active surface of the lowerelectronic device 3A is facing an active surface of the electronicdevice (e.g., the first electronic device 3 and/or the second electronicdevice 3B). The lower electronic device 3A may be electrically connectedto the first electronic device 3 and the second electronic device 3Bthrough the first wiring structure 2. In some embodiments, the lowerelectronic device 3A is bonded to and electrically connected to thefirst wiring structure 2 by the conductive bumps 61. In someembodiments, the first wiring structure 2 is between the electronicdevice(s) (e.g., the first electronic device 3 and/or the secondelectronic device 3B) and the lower electronic device 3A. In someembodiments, the lower electronic device 3A may be referred to as abridge device, and the first electronic device 3 and the secondelectronic device 3B are electrically connected to each other throughthe lower electronic device 3A.

The molding compound 43 encapsulates the lower electronic device 3A. Insome embodiments, the molding compound 43 and the encapsulant 13 may beor include the same or different materials. In some embodiments, thefirst wiring structure 2 is disposed on the molding compound 43.

The second wiring structure 41 may be disposed on a bottom surface ofthe molding compound 43. In some embodiments, at least one bonding pad411 is disposed in the second wiring structure 41. In some embodiments,the bonding pad 411 extends through the second wiring structure 41. Insome embodiments, the second wiring structure 41 may be electricallyconnected to the first wiring structure 2 through at least oneconductive pillar 44. In some embodiments, the conductive pillar 44extends through the molding compound 43 to connect to the bonding pad411. In some embodiments, the lower electronic device 3A is disposedbetween the second wiring structure 41 and the first wiring structure 2.In some embodiments, the lower electronic device 3A is disposed on thesecond wiring structure 41. In some embodiments, the lower electronicdevice 3A is attached to the second wiring structure 41 through anadhesion layer 46. In some embodiments, a bonding pad (e.g., the bondingpad 411 and) is disposed on a side of the second wiring structure 41opposite to the lower electronic device 3A.

The substrate structure 5 may be connected to the second wiringstructure 41 through at least two bonding structures (e.g., at least onefirst bonding structure 51 and at least one second bonding structure52), and the at least two bonding structures 51, 52 respectively includedifferent materials. In some embodiments, the different materials of theat least two bonding structures 51, 52 have different melting points.

The first bonding structure 51 and the second bonding structure 52respectively include different materials. In some embodiments, the firstbonding structure 51 includes a first bonding material, and the secondbonding structure 52 includes a second bonding material different fromthe first bonding material. In some embodiments, a melting point of thefirst bonding material is higher than a melting point of the secondbonding material. In some embodiments, the first bonding materialincludes a gold-tin (AuSn) alloy, and the second bonding materialincludes copper (Cu). In some embodiments, the first bonding materialincludes silver (Ag) paste, copper (Cu) paste, or a combination thereof,and the second bonding material includes tin (Sn).

In some embodiments, as shown in FIG. 7, the first bonding structure 51includes a first bonding pad 513 disposed in the substrate structure 5.In some embodiments, the first bonding pad 513 may be a portion of acircuit layer in the substrate structure 5. In some embodiments, thefirst bonding structure 51 includes a first bonding solder 512 disposedbetween the substrate structure 5 and a bonding pad of the second wiringstructure 41. In some embodiments, the first bonding solder 512 isdisposed between the first bonding pad 513 and the bonding pad 411 ofthe second wiring structure 41. In some embodiments, the first bondingsolder 512 and/or the first bonding pad 513 includes the first bondingmaterial.

In some embodiments, as shown in FIG. 7, the second bonding structure 52includes a second bonding pad 523 disposed in the substrate structure 5.In some embodiments, the second bonding pad 523 may be a portion of acircuit layer in the substrate structure 5. In some embodiments, thesecond bonding structure 52 includes a second bonding solder 522disposed between the substrate structure 5 and a bonding pad of thesecond wiring structure 41. In some embodiments, the second bondingsolder 522 is disposed between the second bonding pad 523 and thebonding pad 411 of the second wiring structure 41. In some embodiments,the second bonding solder 522 and/or the second bonding pad 523 includesthe second bonding material.

In some embodiments, the first bonding solder 512 of the first bondingstructure 51 includes the first bonding material, and the second bondingsolder 522 of the second bonding structure 52 includes the secondbonding material. In some embodiments, the first bonding material of thefirst bonding solder 512 may be or include silver (Ag) paste, copper(Cu) paste, or a combination thereof, and the second bonding material ofthe second bonding solder 522 may be or include tin (Sn).

The underfill 45 is disposed in a space between the substrate structure5 and the second wiring structure 41 to cover and protect the firstbonding structure 51 and the second bonding structure 52. In someembodiments, the underfill 45 directly contacts the first bondingstructure 51 and the second bonding structure 52.

In some embodiments, the first electrical path 33 extends through theencapsulant 13. In some embodiments, the second electrical path 34extends through the encapsulant 13 and is located between the firstelectrical path 33 and the first electronic device 3. In someembodiments, the first electrical path 33 and the second electrical path34 further extend through the first wiring structure 2. In someembodiments, the first electrical path 33 and the second electrical path34 further extend through the molding compound 43. In some embodiments,the first electrical path 33 and the second electrical path 34 areelectrically connected to the bonding pad 411. In some embodiments, thefirst electrical path 33 and the second electrical path 34 physicallycontact the bonding pad 411.

The first electrical path 33 may have an end 33 a and an end 33 bopposite the end 33 a, and the second electrical path 34 may have an end34 a and an end 34 b opposite the end 34 a. In some embodiments, the end33 a and the end 34 a are facing away from the first wiring structure 2.In some embodiments, the end 33 a of the first electrical path 33 andthe end 34 a of the second electrical path 34 are exposed from thesurface 131 of the encapsulant 13. In some embodiments, the end 33 b ofthe first electrical path 33 and the end 34 b of the second electricalpath 34 are connected to the same bonding pad 411. In some embodiments,the first electrical path 33, the second electrical path 34, and thefirst bonding solder 512 of the first bonding structure 52 directlycontact the bonding pad 411 of the second wiring structure 41.

FIG. 8 illustrates a cross-sectional view of a package structure 1 eaccording to some embodiments of the present disclosure. The packagestructure 1 e includes a first wiring structure 2, a first electronicdevice 3, a second electronic device 3B, a lower electronic device 3A, asubstrate structure 5, at least one first joint structure 11, at leastone second joint structure 12, a encapsulant 13, an underfill 15, afirst conductive path 53, a second conductive path 54, a second wiringstructure 41, a molding compound 43, an underfill 45, and at least twobonding structures 51A, 52. In some embodiments, the first wiringstructure 2, the first electronic device 3, the second electronic device3B, the lower electronic device 3A, the substrate structure 5, the firstjoint structure 11, the second joint structure 12, the encapsulant 13,the underfill 15, the second wiring structure 41, the molding compound43 and the underfill 45 are similar to those shown in previous drawing(e.g., FIG. 1A, FIG. 2, FIG. 4A, FIG. 5 and FIG. 7), and the details ofwhich are omitted hereinafter.

In some embodiments, as shown in FIG. 8, the first bonding structure 51Aincludes a first bonding bump 511A disposed on the bonding pad 411, afirst bonding pad 513 disposed in the substrate structure 5, and a firstbonding solder 512A disposed between the first bonding pad 513 and thefirst bonding bump 511A. In some embodiments, the first bondingstructure 51A may further include a first bonding layer 514 between thefirst bonding pad 513 and the first bonding solder 512A. In someembodiments, the first bonding bump 511A, the first bonding solder 512A,the first bonding layer 514, and/or the first bonding pad 513 includesthe first bonding material, and the second bonding solder 522 and/or thesecond bonding pad 523 includes the second bonding material. In someembodiments, a bonding pad (e.g., the first bonding pad 513) of thefirst bonding structure 51A is disposed on a side of the second wiringstructure 41 opposite to the lower electronic device 3A.

In some embodiments, as shown in FIG. 8, the first bonding structure 51Aand the second bonding structure 52 have different structures. Forexample, the second bonding structure 52 does not include a bonding bumpbetween the second bonding solder 522 and the bonding pad 411. In someembodiments, the first bonding solder 512A and the second bonding solder522 have different shapes. The detailed structure of the first bondingstructure 51A is similar to that of the first joint structure 11A ofFIG. 4A and FIG. 5, and the details are omitted hereinafter.

In some embodiments, the first bonding material of the first bondingbump 511A may be or include a gold-tin (AuSn) alloy. In someembodiments, the first bonding material of the first bonding layer 514may be or include a gold-tin (AuSn) alloy. In some embodiments, thefirst bonding solder 512A and the second bonding solder 522 may both beor include tin (Sn).

In some embodiments, as shown in FIG. 8, the substrate structure 5includes two conductive paths (e.g., a first conductive path 53 and asecond conductive path 54) respectively connected to an end 53 a of aconductive via and an end 54 a of a conductive via, the end 53 a and theend 54 a are exposed from a surface 57 (also referred to as “an uppersurface”) of the substrate structure 5, and the first conductive path 53and the second conductive path 54 are both connected to the firstbonding pad 513. In some embodiments, the first conductive path 53includes an inner via connected to the first bonding pad 513, a circuitlayer 522A, a circuit layer 521B, and an inner via connecting thecircuit layer 522A to the circuit layer 521B. In some embodiments, thesecond conductive path 54 includes a circuit layer 521A. In someembodiments, the first conductive path 53 and the second conductive path54 physically contact the first bonding pad 513.

FIG. 9A, FIG. 9B, FIG. 9C and FIG. 9D illustrate top views of portionsof various package structures according to some embodiments of thepresent disclosure. It is to be noted that several elements are omittedin these drawings to more clearly illustrate the features of the presentembodiments.

As shown in FIG. 9A, in some embodiments, the package structure mayinclude a plurality of the first joint structures 11, and the firstjoint structures 11 may be located corresponding to a peripheral regionof the first electronic device 3 from a top view. In some embodiments,also referring to, for example, FIG. 1A, the first bump 111 may belocated corresponding to a peripheral region of the electronic device 3from a top view. In some embodiments, also referring to, for example,FIG. 1A, the first solder 112 may be located corresponding to aperipheral region of the electronic device 3 from a top view. In someembodiments, also referring to, for example, FIG. 1A, the first pad 113may be located corresponding to a peripheral region of the electronicdevice 3 from a top view.

In some embodiments, as shown in FIG. 9A, the first joint structures 11may be located in regions 11P adjacent to the corners of the firstelectronic device 3 from a top view. In some embodiments, the secondjoint structures 12 may be located in some regions other than theregions 11P. For example, the second joint structures 12 may be locatedbetween the regions 11P. In some embodiments, each region 11P may bedisposed with four or more first joint structures 11.

As shown in FIG. 9B, in some embodiments, the first joint structures 11may be located corresponding to a central region of the first electronicdevice 3 from a top view. For example, the first joint structures 11 maybe located in regions 11C adjacent to the center of the first electronicdevice 3 from a top view. In some embodiments, the second jointstructures 12 may be located in some regions other than the region 11C.For example, the second joint structures 12 may be located correspondingto a peripheral region of the first electronic device 3 from a top view.In some embodiments, each region 11C may be disposed with four or morefirst joint structures 11.

As shown in FIG. 9C, in some embodiments, the first joint structures 11may be located corresponding to a peripheral region of the firstelectronic device 3 from a top view. For example, the first jointstructures 11 may be located in a region 11R which corresponds to theperipheral region and surrounds the central region of the firstelectronic device 3. In some embodiments, the second joint structures 12may be located in the central region of the first electronic device 3and surrounded by the first joint structures 11 from a top view. In someembodiments, the region 11R may be disposed with ten or more first jointstructures 11.

As shown in FIG. 9D, in some embodiments, the first joint structures 11may be located corresponding to a region including a power pad and/or aground pad of the first electronic device 3. In some embodiments, thefirst joint structures 11 may be located in the region 11P1 which iscorresponding to a peripheral region of the first electronic device 3and includes a power pad and/or a ground pad. Since I/O counts arehigher in the region including a power pad and/or a ground pad, thefirst joint structures 11 located in the region 11P1 may further balancethe stress and reduce the warpage level.

In some embodiments, as shown in FIG. 9D, the package structure mayfurther include one or more second electronic devices 3B disposedadjacent to a lateral side of the first electronic device 3, and theregion 11P1 including a power pad and/or a ground pad is opposite thelateral side adjacent to the second electronic devices 3B. In someembodiments, the first joint structures 11 may be further located in aregion 11P2 corresponding to the peripheral region of the firstelectronic device 3 and opposite the region 11P1, and the secondelectronic devices 3B are disposed adjacent to the region 11P2. In someembodiments, a number of the first joint structures 11 in the regions11P2 may be less than a number of the first joint structures 11 in theregion 11P1.

In some embodiments, as shown in FIG. 9D, the first joint structures 11may be located corresponding to a peripheral region of a combination ofthe first electronic device 3 and the second electronic device 3B. Insome embodiments, the first joint structures 11 may be located in aregion 11P1 adjacent to a lateral side of the first electronic device 3and in regions 11P3 adjacent to lateral sides of second the electronicdevice 3B from a top view. In some embodiments, the first bump 111 maybe located corresponding to a peripheral region of a combination of thefirst electronic device 3 and the second electronic device 3B. In someembodiments, the first solder 112 may be located corresponding to aperipheral region of a combination of the first electronic device 3 andthe second electronic device 3B. In some embodiments, the first pad 113may be located corresponding to a peripheral region of a combination ofthe first electronic device 3 and the second electronic device 3B.

FIG. 10A, FIG. 10B, FIG. 10C, FIG. 10D, FIG. 10E and FIG. 10F illustratevarious stages of a method of manufacturing a package structure 1according to some embodiments of the present disclosure.

Referring to FIG. 10A, a carrier 101 is provided, and a release layer102 is formed on the carrier 101.

Referring to FIG. 10B, a first wiring structure 2 is formed or providedon the release layer 102. In some embodiments, the first wiringstructure 2 may be formed by forming a plurality of dielectric layers, aplurality of inner vias in the dielectric layers, and a plurality ofcircuit layer between the dielectric layers and connected to thecorresponding inner vias. For example, a dielectric layer 215 may beformed on the release layer 102, inner vias may be formed in thedielectric layer 215, and a circuit layer 224 may be formed on thedielectric layer 215 and connected to the inner vias, so as to form aredistribution layer of the first wiring structure 2. In theembodiments, the first wiring structure 2 may be formed by repeating theoperation of forming the above dielectric layer 215, the inner vias andthe circuit layer 224. In the embodiments, the first pad 113 and thesecond pad 123 are portions of the circuit layer 221.

Referring to FIG. 10C, one or more first solders 112 are formed on thefirst pads 113, and one or more second solders 122 are formed on thesecond pads 123. In some embodiments, the first solder 112 includes afirst material, and the second solder 122 includes the second material.In some embodiments, the first material of the first solder 112 may beor include silver (Ag) paste, copper (Cu) paste, or a combinationthereof, and the second material of the second solder 122 may be orinclude tin (Sn). A melting point of the first material the first solder112 may be higher than the second material of the second solder 122.

Referring to FIG. 10D, at least one electronic device (e.g., the firstelectronic device 3 and/or the second electronic device 3B) is provided.In some embodiments, the electronic device (e.g., the first electronicdevice 3 and/or the second electronic device 3B) may include one or morefirst bumps 111 and one or more second bumps 121.

Referring to FIG. 10E, the electronic device (e.g., the first electronicdevice 3 and/or the second electronic device 3B) is bonded to the firstwiring structure 2 through one or more first joint structures 11 under afirst temperature. In some embodiments, the electronic device (e.g., thefirst electronic device 3 and/or the second electronic device 3B) isdisposed on the first wiring structure 2, and a first heating process H1is conducted to form one or more first joint structures 11. In theembodiments, the first bump 111 contacts the first solder 112, and thesecond bump 121 contacts the second solder 122. In some embodiments, thefirst heating process H1 is conducted on the first bump 111, the firstsolder 112, and the first pad 113. In some embodiments, the firstheating process H1 is conducted under the first temperature. In someembodiments, the first temperature is higher than the melting point ofthe second bump 121, the melting point of the second solder 122, and themelting point of the second pad 123. In some embodiments, the firstheating process H1 is conducted under the first temperature that ishigher than about 270° C. In some embodiments, the first heating processH1 is conducted by a laser technique to melt the first solder 112. Insome embodiments, after the first heating process H1 is conducted, theat least one first joint structure 11 is formed, while the second jointstructure 12 is not formed yet.

In some embodiments, a mask 601 is arranged to define at least oneopening 602 corresponding to a predetermined position of theto-be-formed first joint structure 11. In some embodiments, the mask 601defines one or more openings 602 that correspond to the first bump 111,the first solder 112, and the first pad 113 from a top view. In someembodiments, the opening 602 is disposed right above the first bump 111,the first solder 112, and the first pad 113. In some embodiments, thefirst heating process is conducted through the opening 602. In someembodiments, the first heating process H1 is conducted through theopening 602 on the first bump 111, the first solder 112, and the firstpad 113. In some embodiments, the mask 601 may prevent the first heatingprocess H1 from being conducted on the second bump 121, the secondsolder 122, and the second pad 123. In some embodiments, the mask 601may be or include stainless steel.

Referring to FIG. 10F, the electronic device (e.g., the first electronicdevice 3 and/or the second electronic device 3B) is bonded to the firstwiring structure 2 through one or more second joint structures 12 undera second temperature. In some embodiments, a second heating process H2is conducted to form one or more second joint structures 12. In someembodiments, the second heating process H2 is conducted after the mask601 is removed. In some embodiments, the first temperature of the firstheating process H1 is higher than the second temperature of the secondheating process H2. In some embodiments, the second heating process H2is conducted under the second temperature that is lower than the meltingpoint of the first bump 111, the melting point of the first solder 112,and/or the melting point of the first pad 113. In some embodiments, thesecond heating process H2 is conducted after conducting the firstheating process H1. In some embodiments, the second heating process H2is conducted for a longer time period than that of the first heatingprocess H1. In some embodiments, the second heating process H2 isconducted by a mass reflow process to melt the second solder 122. It isnoted that the first joint structure 11 remains in a solid state underthe second temperature. As such, the electronic device (e.g., the firstelectronic device 3 and/or the second electronic device 3B) is bonded tothe first wiring structure 2. Then, the carrier 101 and the releaselayer 102 are removed. Then, a singulation process is conducted so as toobtain the package structure 1 shown in FIG. 1A.

According to some embodiments of the present disclosure, the firstwiring structure 2 and the electronic device (e.g., the first electronicdevice 3 and/or the second electronic device 3B) are bonded together byutilizing two different heating temperatures to form two different jointstructures (e.g., the first joint structure 11 and the second jointstructure 12) between the first wiring structure 2 and the electronicdevice (e.g., the first electronic device 3 and/or the second electronicdevice 3B) in two different steps. As such, after the first jointstructure 11 having a higher melting point is formed on chosen localregions, the relative position between the first wiring structure 2 andthe electronic device (e.g., the first electronic device 3 and/or thesecond electronic device 3B) can be stably fixed. Then the second jointstructure 12 can be formed under a relatively lower temperatureperformed for a relatively longer time, which facilitates the formationof intermetallic compound (IMC), such that the overall bonding strengthof the package structure 1 can be increased.

In addition, according to some embodiments of the present disclosure,the laser process in the first heating process H1 provides a relativelyhigh heat, high precision and a relatively short processing time, andthe following mas reflow process in the second heating process H2 can beconducted for a relatively long time to significantly increase thestructural strength of the first joint structure 11.

Moreover, according to some embodiments of the present disclosure, thefirst heating process H1 is only performed on local regions, despite thefirst temperature of the first heating process H1 is higher than thesecond temperature of the second heating process H2, the heat applied inthe first heating process H1 is still relatively low and thus does notcause serious warpage and/or shrinkage to the first wiring structure 2and/or the electronic device (e.g., the first electronic device 3 and/orthe second electronic device 3B). Accordingly, the precision of thealignment of the bonding process is not affected while the jointstrength still can be increased.

Furthermore, according to some embodiments of the present disclosure,the first joint structure 11 does not melt or deform when the secondheating process H2 is conducted, such that the size of the space betweenthe first wiring structure 2 and the electronic device (e.g., the firstelectronic device 3 and/or the second electronic device 3B) (alsoreferred to as “a die gap”) is not affected by the second heatingprocess H2, the overall structure of the package structure 1 is stable,and the quality of the as-formed package structure 1 is furtherimproved.

FIG. 11A, FIG. 11B and FIG. 11C illustrate various stages of a method ofmanufacturing a package structure 1 a according to some embodiments ofthe present disclosure.

First, operations as illustrated in FIGS. 10A-10D are performed. Next,referring to FIG. 11A, the electronic device (e.g., the first electronicdevice 3 and/or the second electronic device 3B) is disposed on thefirst wiring structure 2.

Next, still referring to FIG. 11A, a patterned mask layer 4 is formed onthe electronic device (e.g., the first electronic device 3 and/or thesecond electronic device 3B). In some embodiments, the patterned masklayer 4 has one or more openings 401 to expose the first bump 111, thefirst solder 112 and the first pad 113 from a top view. In someembodiments, the patterned mask layer 4 directly contacts the surface 31of the first electronic device 3 (and/or the upper surface of the secondelectronic device 3B).

Referring to FIG. 11B, operations similar to those illustrated in FIG.10E may be performed on the first bump 111, the first solder 112 and thefirst pad 113. In some embodiments, the first heating process H1 isconducted on the first bump 111, the first solder 112 and the first pad113 through the opening 401 of the patterned mask layer 4. The patternedmask layer 4 prevents the first heating process H1 from being conductedon the second pad 121, the second solder 122, and the second pad 123. Insome embodiments, the first heating process H1 is conducted by a lasertechnique to melt the first solder 112.

Referring to FIG. 11C, operations similar to those illustrated in FIG.10F may be performed on the second pad 121, the second solder 122, andthe second pad 123. In some embodiments, the second heating process H2is conducted after conducting the first heating process H1. In someembodiments, the second heating process H2 is conducted by a mass reflowprocess to melt the second solder 122. It is noted that the first jointstructure 11 remains in a solid state under the second temperature. Assuch, the electronic device (e.g., the first electronic device 3 and/orthe second electronic device 3B) is bonded to the first wiring structure2, and then the package structure 1 a shown in FIG. 3 may be formed. Insome embodiments, a grounding process performed on the encapsulant 13may expose the first electronic device 3 and also remove the patternedmask layer 4, so as to form the package structure 1 shown in FIG. 1A.

FIG. 12A, FIG. 12B, FIG. 12C, FIG. 12D, FIG. 12E, FIG. 12F, FIG. 12G,FIG. 12H, FIG. 12I and FIG. 12J illustrate various stages of a method ofmanufacturing a package structure according to some embodiments of thepresent disclosure.

Referring to FIG. 12A, a carrier 101 is provided, and a release layer102 is formed on the carrier 101.

Referring to FIG. 12B, a second wiring structure 41 is formed on therelease layer 102, and a plurality of conductive pillars 44, 331 and 341are formed on the second wiring structure 41. In some embodiments, aplurality of bonding pads 411 are formed in the second wiring structure41, and the conductive pillars 44, 331 and 341 are connected to thebonding pads 411.

Referring to FIG. 12C, a lower electronic device 3A is disposed on thesecond wiring structure 41. In some embodiments, the lower electronicdevice 3A is attached to the second wiring structure 41 through anadhesion layer 46. The lower electronic device 3A may include one ormore conductive bumps 61.

Referring to FIG. 12D, a molding compound 43 is formed to encapsulatethe lower electronic device 3A. In some embodiments, the moldingcompound 43 encapsulates the conductive pillars 44, 331 and 341 and theconductive bumps 61.

Referring to FIG. 12E, a first wiring structure 2 is formed or disposedon the molding compound 43 to electrically connect the first wiringstructure 2 to the second wiring structure 41. In some embodiments, thefirst wiring structure 2 may be formed by operations similar to thoseillustrated in FIG. 10B. For example, a dielectric layer 215 may beformed on the molding compound 43 and the lower electronic device 3A,inner vias may be formed in the dielectric layer 215 and on theconductive bumps 61 and the conductive pillars 44, and a circuit layer224 may be formed on the dielectric layer 215 and connected to the innervias, so as to form a redistribution layer of the first wiring structure2. The first wiring structure 2 may be formed by repeating the operationof forming the above dielectric layer 215, the inner vias and thecircuit layer 224. In some other embodiments, the first wiring structure2 may be formed in advance, and then a bonding process may be performedby connecting some of the exposed inner vias of the first wiringstructure 2 to the conductive pillars 44 and the conductive bumps 61. Insome embodiments, conductive pillars 332 and 342 are formed in the firstwiring structure 2, and the conductive pillars 332 and 342 arerespectively connected to the conductive pillars 331 and 342. Next, insome embodiments, conductive pillars 333 and 334 are respectively formedon the conductive pillars 332 and 342. As such, a first electrical path33 including the conductive pillars 331, 332 and 333 is formed, and asecond electrical path 34 including the conductive pillars 341, 342 and343 is formed.

Referring to FIG. 12F, at least one electronic device (e.g., the firstelectronic device 3 and/or the second electronic device 3B) is provided,and the electronic device (e.g., the first electronic device 3 and/orthe second electronic device 3B) is bonded to the first wiring structure2 through at least two joint structures (e.g., the first joint structure11 and the second joint structure 12). In some embodiments, theelectronic device (e.g., the first electronic device 3 and/or the secondelectronic device 3B) is bonded to the first wiring structure 2 byoperations similar to those illustrated in FIGS. 10E-10F or FIGS.11B-11C, and the details are omitted hereinafter.

Still referring to FIG. 12F, an encapsulant 13 is formed to encapsulatethe electronic device (e.g., the first electronic device 3 and/or thesecond electronic device 3B) and the conductive pillars 333 and 343. Assuch, the as-formed first electrical path 33 and the second electricalpath 34 extend through the encapsulant 13, the first wiring structure 2,and the molding compound 43.

Referring to FIG. 12G, the carrier 101 and the release layer 102 areremoved.

Referring to FIG. 12H, one or more first bonding bumps 511A and one ormore second bonding solders 522 are formed on the bonding pads 411.

Referring to FIG. 12I, a substrate structure 5 is provided. In someembodiments, the substrate structure 5 may include a plurality ofdielectric layer and a plurality of circuit layer. In some embodiments,the substrate structure 5 may be a substrate level conductive structure.In some embodiments, the substrate structure 5 may further include acore portion including Ajinomoto build-up film (ABF),bismaleimide-triazine (BT) or epoxy resin.

Still referring to FIG. 12I, one or more first bonding layers 514 areformed on the substrate structure 5, and one or more first bondingsolders 512A may be formed on the first bonding layers 514. In someembodiments, the first bonding solders 512A may be omitted. In someembodiments, one or more first bonding pads 513 and one or more secondbonding pads 523 are formed in the substrate structure 5. In someembodiments, the first bonding pad(s) 513 and the second bonding pad(s)523 may be portions of one or more circuit layers in the substratestructure 5.

Referring to FIG. 12J, the second wiring structure 41 is bonded to thesubstrate structure 5. In some embodiments, the bonding pad 411 contactsthe first bonding bump 511A, and the first bonding bump 511A contactsthe first bonding solder 512A and the first bonding layer 514. In someembodiments, the bonding pad 411 contacts the second bonding solder 522,and the second bonding solder 522 contacts the second bonding pad 523.In some embodiments, a first bonding process is conducted to form one ormore first bonding structures 51A, and a second bonding process isconducted to form one or more second bonding structures 52.

In some embodiments, the first bonding process is conducted by a weldingtechnique. In some embodiments, a welding current is applied through thefirst electrical path 33 and the second electrical path 34 so as toprovide heat to the bonding pad 411 and then to the first bonding bump511A, the first bonding solder 512A, the first bonding layer 514, andthe first bonding pad 513, so that the first bonding structure 51A isformed. In some embodiments, the welding current is applied on the end33 a and the end 34 a. The predetermined location of the first bondingstructure 51A is relatively distant from the surface 131 (also referredto as “the upper surface”) of the encapsulant 13 with many interveninglayers/structures therebetween, and providing heat to such location fromoutside, for example, applying laser from outside the encapsulant 13,can be very difficult. According to some embodiments of the presentdisclosure, the welding process conducted utilizing conductive paths(e.g., the first conductive path 33 and the second conductive path 34)extending through the package structure can effectively provide heat tothe first bonding bump 511A, the first bonding solder 512A, the firstbonding layer 514, and the first bonding pad 513, the bonding processcan be made simple, and thus the yield of the manufacturing process ofthe package structure can be improved.

In some embodiments, the second bonding process is conducted afterconducting the first bonding process. In some embodiments, the secondbonding process is conducted by a mass reflow process. In someembodiments, a temperature of the first bonding process is higher than atemperature of the second bonding process. Then, an underfill 45 may bedisposed in a space between the substrate structure 5 and the secondwiring structure 41 to cover and protect the first bonding structure 51Aand the second bonding structure 52. As such, a package structure havinga structure similar to that of the package structure 1 d shown in FIG. 7except the first bonding structure 51 being replaced by the firstbonding structure 51A shown in FIG. 8 may be formed.

FIG. 13 illustrates an intermediate stage of a method of manufacturing apackage structure according to some embodiments of the presentdisclosure.

First, operations similar to those illustrated in FIGS. 12A-12H areperformed, expect that the first electrical path 33 and the secondelectrical path 34 are omitted.

Next, referring to FIG. 13, a substrate structure 5 including a firstconductive path 53 and a second conductive path 54 is provided. Then,the second wiring structure 41 is bonded to the substrate structure 5 byoperations similar to those illustrated in FIG. 12J, except that thefirst bonding process in the present embodiment is different from thatillustrated in FIG. 12J. In some embodiments, as shown in FIG. 13, thefirst bonding process is conducted by a welding technique. In someembodiments, a welding current is applied through the first conductivepath 53 and the second conductive path 54 so as to provide heat to thefirst bonding solder 512 and the first bonding pad 513, so that thefirst bonding structure 51 is formed. In some embodiments, the weldingcurrent is applied on the end 53 a and the end 54 a.

Then, a second bonding process is conducted after conducting the firstbonding process. In some embodiments, the second bonding process isconducted by a mass reflow process. Then, an underfill 45 may bedisposed in a space between the substrate structure 5 and the secondwiring structure 41 to cover and protect the first bonding structure 51and the second bonding structure 52. As such, a package structure havinga structure similar to that of the package structure 1 e shown in FIG. 8except the first bonding structure 51A being replaced by the firstbonding structure 51 shown in FIG. 7 may be formed.

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,”“down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,”“lower,” “upper,” “over,” “under,” and so forth, are indicated withrespect to the orientation shown in the figures unless otherwisespecified. It should be understood that the spatial descriptions usedherein are for purposes of illustration only, and that practicalimplementations of the structures described herein can be spatiallyarranged in any orientation or manner, provided that the merits ofembodiments of this disclosure are not deviated from by such anarrangement.

As used herein, the terms “approximately,” “substantially,”“substantial” and “about” are used to describe and account for smallvariations. When used in conjunction with an event or circumstance, theterms can refer to instances in which the event or circumstance occursprecisely as well as instances in which the event or circumstance occursto a close approximation. For example, when used in conjunction with anumerical value, the terms can refer to a range of variation less thanor equal to ±10% of that numerical value, such as less than or equal to±5%, less than or equal to ±4%, less than or equal to ±3%, less than orequal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%,less than or equal to ±0.1%, or less than or equal to ±0.05%. Forexample, two numerical values can be deemed to be “substantially” thesame or equal if a difference between the values is less than or equalto ±10% of an average of the values, such as less than or equal to ±5%,less than or equal to ±4%, less than or equal to ±3%, less than or equalto ±2%, less than or equal to ±1%, less than or equal to ±0.5%, lessthan or equal to ±0.1%, or less than or equal to ±0.05%.

Two surfaces can be deemed to be coplanar or substantially coplanar if adisplacement between the two surfaces is no greater than 5 μm, nogreater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

As used herein, the singular terms “a,” “an,” and “the” may includeplural referents unless the context clearly dictates otherwise.

As used herein, the terms “conductive,” “electrically conductive” and“electrical conductivity” refer to an ability to transport an electriccurrent. Electrically conductive materials typically indicate thosematerials that exhibit little or no opposition to the flow of anelectric current. One measure of electrical conductivity is Siemens permeter (S/m). Typically, an electrically conductive material is onehaving a conductivity greater than approximately 10⁴ S/m, such as atleast 10⁵ S/m or at least 10⁶ S/m. The electrical conductivity of amaterial can sometimes vary with temperature. Unless otherwisespecified, the electrical conductivity of a material is measured at roomtemperature.

Additionally, amounts, ratios, and other numerical values are sometimespresented herein in a range format. It is to be understood that suchrange format is used for convenience and brevity and should beunderstood flexibly to include numerical values explicitly specified aslimits of a range, but also to include all individual numerical valuesor sub-ranges encompassed within that range as if each numerical valueand sub-range is explicitly specified.

While the present disclosure has been described and illustrated withreference to specific embodiments thereof, these descriptions andillustrations are not limiting. It should be understood by those skilledin the art that various changes may be made and equivalents may besubstituted without departing from the true spirit and scope of thepresent disclosure as defined by the appended claims. The illustrationsmay not be necessarily drawn to scale. There may be distinctions betweenthe artistic renditions in the present disclosure and the actualapparatus due to manufacturing processes and tolerances. There may beother embodiments of the present disclosure which are not specificallyillustrated. The specification and drawings are to be regarded asillustrative rather than restrictive. Modifications may be made to adapta particular situation, material, composition of matter, method, orprocess to the objective, spirit and scope of the present disclosure.All such modifications are intended to be within the scope of the claimsappended hereto. While the methods disclosed herein have been describedwith reference to particular operations performed in a particular order,it will be understood that these operations may be combined,sub-divided, or re-ordered to form an equivalent method withoutdeparting from the teachings of the present disclosure. Accordingly,unless specifically indicated herein, the order and grouping of theoperations are not limitations of the present disclosure.

What is claimed is:
 1. A package structure, comprising: a first wiringstructure; and at least one electronic device connected to the firstwiring structure through at least two joint structures, the at least twojoint structures respectively including different materials.
 2. Thepackage structure as claimed in claim 1, wherein the at least two jointstructures includes at least one first joint structure including a firstmaterial and at least one second joint structure including a secondmaterial, and a melting point of the first material is higher than amelting point of the second material.
 3. The package structure asclaimed in claim 2, wherein the at least two joint structures eachincludes a first bump and a second bump disposed on the electronicdevice, the first bump includes the first material, and the second bumpincludes the second material.
 4. The package structure as claimed inclaim 3, wherein the first bump is located corresponding to a peripheralregion of the electronic device from a top view.
 5. The packagestructure as claimed in claim 4, wherein the at least one electronicdevice includes a first electronic device and a second electronic devicearranged side by side, and the first bump is located corresponding to aperipheral region of a combination of the first electronic device andthe second electronic device.
 6. The package structure as claimed inclaim 3, wherein the first material of the first bump includes agold-tin (AuSn) alloy, and the second material of the second bumpincludes copper.
 7. The package structure as claimed in claim 2, whereinthe at least two joint structures each includes a first solder and asecond solder disposed between the first wiring structure and a bump ofthe electronic device, the first solder includes the first material, andthe second solder) includes the second material.
 8. The packagestructure as claimed in claim 7, wherein the first solder is locatedcorresponding to a peripheral region of the electronic device from a topview.
 9. The package structure as claimed in claim 8, wherein the atleast one electronic device includes a first electronic device and asecond electronic device arranged side by side, and the first solder islocated corresponding to a peripheral region of a combination of thefirst electronic device and the second electronic device.
 10. Thepackage structure as claimed in claim 7, wherein the first material ofthe first solder includes silver (Ag) paste, copper (Cu) paste, or acombination thereof, and the second material of the second solderincludes tin (Sn).
 11. The package structure as claimed in claim 2,wherein the at least two joint structures each includes a first pad anda second pad disposed in the first wiring structure, and the first jointstructure further includes a first conductive layer disposed on thefirst pad.
 12. A package structure, comprising: a first wiringstructure; a first electronic device connected to the first wiringstructure; a second wiring structure; a lower electronic device disposedon the second wiring structure, an active surface of the lowerelectronic device facing an active surface of the first electronicdevice; a molding compound encapsulating the lower electronic device,wherein the first wiring structure is deposed on the molding compound;and a substrate structure connected to the second wiring structurethrough at least two bonding structures, the at least two bondingstructures respectively including different materials.
 13. The packagestructure as claimed in claim 12, further comprising: a bonding paddeposed in the second wiring structure; an encapsulant encapsulating thefirst electronic device; and a first electrical path and a secondelectrical path extending through the encapsulant, the first wiringstructure, and the molding compound, wherein the first electrical pathand the second electrical path physically contact the bonding pad. 14.The package structure as claimed in claim 13, wherein an end of thefirst electrical path and an end of the second electrical path areexposed from an upper surface of the encapsulant.
 15. The packagestructure as claimed in claim 12, wherein the at least two bondingstructures include a first bonding structure including a first boningmaterial, and a second bonding structure including a second boningmaterial, and a melting point of the first bonding material is higherthan a melting point of the second bonding material.
 16. The packagestructure as claimed in claim 12, further comprising: a bonding paddeposed on a side of the second wiring structure opposite to the lowerelectronic device; wherein the substrate structure includes a firstconductive path and a second conductive path physically contacting thebonding pad, and an end of the first conductive path and an end of thesecond conductive path are exposed from an upper surface of thesubstrate structure.
 17. A method for manufacturing a package structure,comprising: (a) providing a first wiring structure; (b) providing afirst electronic device on the first wiring structure; (c) bonding thefirst electronic device to the first wiring structure through a firstjoint structure under a first temperature; and (d) bonding the firstelectronic device to the first wiring structure through a second jointstructure under a second temperature, wherein the first temperature ishigher than the second temperature.
 18. The package structure as claimedin claim 17, wherein in (c), the first joint structure is formed byconducting a laser technique.
 19. The package structure as claimed inclaim 17, wherein in (d), the second joint structure is formed byconducting a mass reflow process.
 20. The package structure as claimedin claim 17, wherein (c) includes: (c1) arranging a mask defining atleast one opening corresponding to a predetermined position of the firstjoint structure, wherein a first heating process under the firsttemperature is conducted through the at least one opening.